1. Technical Field
The present invention relates to an asymmetrical multilayer substrate, an RF module, and a method for manufacturing the asymmetrical multilayer substrate, and more particularly, to an asymmetrical multilayer substrate having odd layers of asymmetric structure and forming in high density, an RF module, and a method for manufacturing the asymmetrical multilayer substrate which have an asymmetric structure.
2. Description of the Related Art
Increases in the processing speed and complexity of logic and RF circuits in electronic products, for example, electronic mobile devices maintain a significant trade-off relationship among requirements for costs, material selection, manufacturability, and perfection of signals. In most cases, only two among these requirements are easily achieved in a single design. In the final product, impact of the trade-off requires consideration for the number of stacked-up layers, and requires impedance matching of an overall thickness and transmission lines.
In the typical manufacturing process, a multi-layered substrate is configured of the symmetric number of stacked redistribution layers such as 2-layer, 4-layer, and 6-layer, which are made of a conductive metal reinforced with a typical genetic material, and is realized in a manner such that a ground reference for signal lines and power lines are generated as a pair in order to suppress an EMI (Electro Magnetic Interference). In order to design a high-specification performance package having a small form factor, a plurality of layers are increased to receive a plurality of I/O without compromising system noise, RF loss, and timing margin.
A typical design issue in an HDI substrate is the crosstalk between a plurality of high-speed I/O and I/Q data. This is mainly caused by discontinuity of return paths typically due to impedance mismatch between source and load, and absence of an appropriate reference ground structure. In the typical HDI substrate, this issue may be solved by inserting more layers used as a ground surface on a signal/RF interconnection layer; however, the insertion of the layers may cause an increase in the entire number of substrate build-up, a material thickness, and overall manufacturing costs.